1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a gate driving method and apparatus for a liquid crystal display panel that minimizes deterioration of picture quality caused by a variation in a gate low voltage.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal having a dielectric anisotropy using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel for displaying a picture, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, liquid crystal cells arranged in a matrix type control the light transmittance in accordance with pixel signals to thereby display a picture.
The driving circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the liquid crystal display panel and the driving circuit.
The data driver and the gate driver are separated into a plurality of drive integrated circuits (IC's). Each of the integrated drive IC's is mounted in an opened IC area of a tape carrier package (TCP) or in a base film of the TCP by a chip on film (COF) system, to thereby be connected to the liquid crystal display panel by a tape automated bonding (TAB) system. Alternatively, the drive IC may be directly mounted onto the liquid crystal display panel by a chip on glass (COG) system. The timing controller and the power supply are mounted onto a main printed circuit board (PCB).
The drive IC's connected to the liquid crystal display panel by the TAB system are connected, via the TCP, a sub-PCB (i.e., a gate PCB and a data PCB) and a flexible printed circuit (PCB), to the timing controller and the power supply on the main PCB.
The drive IC's mounted onto the liquid crystal display panel by the COG system are connected, via line on glass (LOG) type signal lines provided at the FPC and the liquid crystal display panel, to the timing controller and the power supply on the main PCB.
Recently, when the drive IC's are connected, via the TCP, to the liquid crystal display panel, the LCD adopts LOG-type signal lines to reduce the number of PCB's, thereby having a thinner thickness. Particularly, the gate PCB delivering a relatively small number of signals is removed, and a plurality of signal lines for applying gate control signals and power signals to the gate drive IC's are provided on the liquid crystal display panel in a LOG type. Thus, the gate drive IC's mounted in the TCP receives the control signals from the timing controller and the power signals from the power supply by way of the main PCB, FPC, the data PCB, the data TCP, the LOG-type signal lines and the gate TCP in turn. In this case, since the gate control signals and the gate power signals applied to the gate drive IC's are distorted by line resistances of the LOG-type signal lines, deterioration in the picture quality displayed on the liquid crystal display panel becomes a problem.
More specifically, as shown in FIG. 1, a LOG-type LCD removed with the gate PCB includes a data PCB 16, a data TCP 12 mounted with a data driving IC 14 and connected between the data PCB 16 and a liquid crystal display panel 6, and a gate TCP 8 mounted with a gate driving IC 10 and connected to the liquid crystal display panel 6.
In the liquid crystal display panel 6, a thin film transistor array substrate 2 and a color filter array substrate 4 are joined to each other with having a liquid crystal therebetween. Such a liquid crystal display panel 6 includes liquid crystal cells defined at intersections between gate lines GL and data lines DL, each of which has a thin film transistor as a switching device. The thin film transistor applies a pixel signals from the data line DL to the liquid crystal cell in response to a scanning signal from the gate line GL.
The data drive IC 14 is connected, via the data TCP 12 and a data pad of the liquid crystal display panel, to the data line DL. The data drive IC 14 converts a digital pixel data into an analog pixel signal to apply it to the data line DL. To this end, the data drive IC 14 receives a data control signal and a pixel data from a timing controller (not shown) and a power signal from a power supply (not shown) by way of the data PCB 16.
The gate drive IC 10 is connected, via the gate TCP 8 and a gate pad of the liquid crystal display panel 6, to the gate line GL. The gate drive IC 10 sequentially applies a scanning signal having a gate high voltage VGH to the gate lines GL. Further, the gate drive IC 10 applies a gate low voltage VGL to the gate lines GL in the remaining interval excluding the time interval when the gate high voltage VGH has been supplied.
To this end, the gate control signals from the timing controller and the power signals from the power supply are applied, via the data PCB 16, to the data TCP 12. The gate control signals and the power signals applied via the data TCP 12 are applied, via a LOG-type signal line group 20 provided at the edge area of the thin film transistor array substrate 2, to the gate TCP 8. The gate control signals and the power signals applied to the gate TCP 8 are inputted, via input terminals of the gate drive IC 10, within the gate drive IC 10. Further, the gate control signals and the power signals are outputted via output terminals of the gate drive IC 10, and applied, via the gate TCP 8 and the LOG-type signal line group 20, to the gate drive IC 10 mounted in the next gate TCP 8.
The LOG-type signal line group 20 is typically comprised of signal lines for supplying direct current driving voltages from the power supply, such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND and a base driving voltage VCC, and gate control signals from the timing controller, such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE.
Such a LOG-type signal line group 20 is formed from the same gate metal layer as the gate lines at a specific pad area of the thin film transistor array substrate 2 in a fine pattern. Thus, the LOG-type signal line group 20 has a larger line resistance than the signal lines on the existent gate PCB. This line resistance distorts gate control signals (i.e., GSP, GSC and GOE) and power signals (i.e., VGH, VGL, VCC, GND and VCOM), thereby causing deterioration in the picture quality such as a horizontal line (i.e., gate dim) 32, cross talk in the dot pattern or a greenish tinge to the color, etc.
FIG. 2 is a view for explaining the horizontal line phenomenon caused by the LOG-type signal line group 20.
Referring to FIG. 2, the LOG-type signal line group 20 is comprised of a first LOG-type signal line group LOG1 connected to an input terminal of a first gate TCP 8, a second LOG-type signal line group LOG2 connected to an input terminal of a second gate TCP 9, and a third LOG-type signal line group LOG3 connected to an input terminal of a third gate TCP 13. The first to third LOG-type signal line groups LOG1 to LOG3 have line resistances aΩ, bΩ and cΩ proportional to the line length thereof, respectively, and are connected, via the gate TCP's 8, 9 and 13, to each other in series.
Thus, the first gate drive IC 10 is supplied with gate control signals GSP, GSC and GOE and power signals VGH, VGL, VCC, GND and VCOM voltage-dropped by the line resistance aΩ of the first LOG-type signal line group LOG1; the second gate drive IC 11 is supplied with those voltage-dropped by the line resistances aΩ+bΩ of the first and second LOG-type signal line groups LOG1 and LOG2; and the third gate drive IC 15 is supplied with those voltage-dropped by the line resistances aΩ+bΩ+cΩ of the first to third LOG-type signal line groups LOG1 to LOG3.
Accordingly, a voltage difference is generated among gate signals VG1 to VG3 applied to the gate lines of first to third horizontal blocks A to C driven with different gate drive IC's 10, 11 and 15, thereby causing horizontal lines 32 among the first to third horizontal line blocks A to C.
FIG. 3 shows a gate signal waveform applied to a plurality of gate lines GLi to GLi+3 included in the liquid crystal display panel 2 shown in FIG. 1.
Each of the gate lines GLi to GLi+3 is maintained at a gate low voltage VGL except for a horizontal period Hi when each gate line is supplied with a gate high voltage VGH upon arriving at a sequence to be scanned. Because a gate insulating film exists at the intersection of the gate line GLi and the data line DL a parasitic capacitor is formed. However, the parasitic capacitor causes instability as the gate low voltage VGL supplied to the gate line GLi is swung in response to a pixel signal applied to the data line DL.
For instance, the gate low voltage VGL is alternately swung toward a positive polarity and a negative polarity every horizontal period in accordance with an average value of pixel signals applied to one horizontal line while alternating a positive polarity and a negative polarity, as shown in FIG. 3, in response to a dot inversion system. Such a swing phenomenon of the gate low voltage VGL is generated similarly at other gate lines to which the gate low voltage VGL is commonly applied via the gate drive IC and the LOG-type signal lines. In this case, a swing width of the gate low voltage is enlarged due to a load amount applied to the gate low voltage VGL, that is, a large parasitic capacitor (i.e., a parasitic capacitor between the gate line and the data line) and a large line resistor of the LOG-type signal line. Such an unstable gate low voltage VGL varies the pixel voltage via a storage capacitor Cst provided between the pixel electrode and the pre-stage gate line. As a result, when a specific dot pattern is displayed by a dot inversion system, a greenish tinge in which a green (G) pixel having a polarity contrary to adjacent red (R) and blue (B) pixels is observed at a relatively large brightness is generated thereby causing deterioration of the picture quality. Furthermore, when a window pattern is displayed using a dot inversion system, horizontal cross talk in which a peripheral area adjacent to the window pattern in a horizontal direction is observed during generation of a relatively large brightness causes deterioration in the picture quality.